1. Field of the Invention
The present invention relates to a driving circuit and a driving method of a matrix type flat panel display device, and a plasma display device using the driving circuit and the driving method.
2. Description of the Related Art
Conventionally, plasma display devices, particularly, AC-driven Plasma Display Panels (PDPs), which are one of matrix type flat panel display devices, come in two types: 2-electrode type PDPs which perform selective discharge (address discharge) and sustain discharge between two electrodes and 3-electrode type PDPs which perform address discharge using a third electrode. Moreover, there are two structure types for the 3-electrode type PDPs. One type has the third electrode being formed on a substrate on which a first electrode and a second electrode to perform sustain discharge therebetween are placed. The other type has the third electrode being formed on another substrate opposite to the substrate of the first and second electrodes.
The aforementioned respective types of PDP devices are based on the same principle of operation, and hence, an example of the structure of the PDP device in which the first and second electrodes to perform sustain discharge therebetween are provided on a first substrate and the third electrode is additionally provided on a second substrate opposite to the first substrate will be explained below.
FIG. 15 is a diagram showing an overall configuration of an AC-driven PDP device. In FIG. 15, the AC-driven PDP device 1 includes plural cells arranged in a matrix form, each cell representing one pixel of a display image. The respective cells are arranged in a matrix with m rows and n columns, as shown by cells Cmn in FIG. 15. In the AC-driven PDP device 1, scan electrodes Y1 to Yn and common electrodes X parallel to each other are provided on a first substrate, and address electrodes A1 to Am are provided in a direction orthogonal to these electrodes Y1 to Yn and X on a second substrate opposite to the first substrate. The common electrodes X are arranged corresponding to and adjacent to the respective scan electrodes Y1 to Yn, and one ends thereof are connected to one another in common.
A common terminal of the common electrodes X is connected to an output terminal of an X-side circuit 2, and the scan electrodes Y1 to Yn are respectively connected to output terminals of a Y-side circuit 3. The address electrodes A1 to Am are connected to output terminals of an address-side circuit 4. The X-side circuit 2 is composed of a circuit which repeats electric discharge. The Y-side circuit 3 is composed of a circuit which performs line-sequential scanning and a circuit which repeats electric discharge. The address-side circuit 4 is composed of a circuit which selects a column to be displayed.
The X-side circuit 2, Y-side circuit 3, and address-side circuit 4 are controlled by control signals supplied from a control circuit 5. Namely, a display operation of the PDP device is carried out by determining which cell to be lighted by the address-side circuit 4 and the circuit which performs line-sequential scanning in the Y-side circuit 3 and then by repeating electric discharge by the X-side circuit 2 and the Y-side circuit 3.
The control circuit 5 generates the control signals based on display data D, a clock CLK indicating a timing at which the display data D is read, a horizontal synchronization signal HS, and a vertical synchronization signal VS which are supplied from the outside, and supplies these control signals to the X-side circuit 2, the Y-side circuit 3, and the address-side circuit 4.
FIG. 16A is a diagram showing a cross sectional structure of a cell Cij at an i-th row and a j-th column as one pixel. In FIG. 16A, the common electrode X and a scan electrode Yi are formed on a front glass substrate 11. Over them, a dielectric layer 12 is deposited as insulation against a discharge space 17. Further, an MgO (magnesium oxide) protective film 13 is deposited over the dielectric layer 12.
On the other hand, an address electrode Aj is formed on a rear glass substrate 14 which is placed opposite the front glass substrate 11. A dielectric layer 15 is deposited over the address electrode Aj. Further, a phosphor 18 is deposited over the dielectric layer 15. Ne+Xe penning gas or the like is filled into a discharge space 17 between the MgO protective film 13 and the dielectric layer 15.
FIG. 16B is a diagram for explaining a capacitance Cp of the AC-driven PDP device. As shown in FIG. 16B, in the AC-driven PDP device, there are capacitive components Ca, Cb, and Cc in the discharge space 17, between the common electrode X and the scan electrode Yi, and in the front glass substrate 11, respectively. A capacitance Cpcell per cell is determined by summing up these capacitive components (Cpcell=Ca+Cb+Cc). A panel capacitance Cp is obtained by summing up the capacitances Cpcell of all cells.
FIG. 16C is a diagram for explaining light emission of the AC-driven PDP device. As shown in FIG. 16C, red, blue, and green phosphors 18 are arranged and painted in a stripe pattern on inner surfaces of ribs 16, and the phosphors 18 are exited by electric discharge between the common electrode X and the scan electrode Y to emit light.
One of methods for reducing the circuit cost of a plasma display device such as described above is a method disclosed in EP Patent Application Publication No. 1065650 and “SID 01 DIGEST”, pp. 1236-1239, “A New Driving Technology for PDPs with Cost Effective Sustain Circuit”. This method is a method in which electric discharge is performed using a potential difference between sustain discharge electrodes by applying a first voltage to one of the sustain discharge electrodes (common electrode X and scan electrode Y) and applying a second voltage different from the first voltage to the other electrode. A circuit to realize this driving method is called a TERES (Technology of Reciprocal Sustainer) circuit.
FIG. 17 is a diagram showing a schematic configuration of the TERES circuit. (Note that only the X-side circuit 2 will be explained, and the Y-side circuit 3 is omitted since it has the same configuration and operation.)
In FIG. 17, a capacitive load 20 (hereinafter referred to as “a load 20”) is the total capacitance of the cells Cmn formed between one common electrode X and one scan electrode Y. The common electrode X and the scan electrode Y are formed in the load 20. The scan electrode Y here is any scan electrode out of the plural scan electrodes Y1 to Yn.
Switches SW1 and SW2 are connected in series between a power supply line with a voltage (Vs/2) supplied from a power supply and a ground (GND). One terminal of a capacitor C1 is connected to an interconnection node between the two switches SW1 and SW2, and a switch SW3 is connected between the other terminal of the capacitor C1 and the ground. Incidentally, a signal line connected to the one terminal of the capacitor C1 is referred to as a first signal line OUTA, and a signal line connected to the other terminal is referred to as a second signal line OUTB.
Switches SW4 and SW5 are connected in series to both the terminals of the capacitor C1. An interconnection node between the two switches SW4 and SW5 is connected to the common electrode X of the load 20 via an output line OUTC.
FIG. 18 is a diagram showing a schematic configuration of the TERES circuit provided with a power recovery circuit in the circuit shown in FIG. 17. In FIG. 18, constituent elements having the same function as those shown in FIG. 17 are designated by the same numerals and symbols, and a duplicate explanation is omitted.
In FIG. 18, a power recovery circuit 21 is connected to the interconnection node between the switches SW4 and SW5, and connected to the common electrode X of the load 20 via the output line OUTC. The power recovery circuit 21 includes two coils L1 and L2 which are connected to the load 20, a switch SW6 connected in series to the coil L1, and a switch SW7 connected in series to the coil L2. The power recovery circuit 21 further includes a capacitor C2 connected between an interconnection node of the two switches SW6 and SW7 and the second signal line OUTB.
The load 20 and the coils L1 and L2 which are connected to the load 20 constitute two serial resonant circuits. In other words, the power recovery circuit 21 has two L-C resonant circuits and recovers electric charge, which was supplied to a panel by resonance between the coil L1 and the load 20, by resonance between the coil L2 and the load 20.
The switches SW1 to SW7 are controlled by the control signals respectively supplied from the control circuit 5 shown in FIG. 15. The control circuit 5 is configured using a logic circuit and the like, and it generates the control signals based on the display data D, the clock CLK, the horizontal synchronization signal HS, the vertical synchronization signal VS, and the like which are supplied from the outside, and supplies these control signals to the switches SW1 to SW7.
FIG. 19 is a time chart showing driving waveforms of a driving circuit of the AC-driven PDP device configured as shown in FIG. 18 during a sustain discharge period. Note that the sustain discharge period is a period in which in order to allow a cell associated with the display data D to emit light and carry out a display operation, electric discharge is performed between the common electrode X and the scan electrode Y in the cell.
In the sustain discharge period, on the common electrode X side, first, the switches SW1, SW3, and SW5 are turned on, and the remaining switches SW2, SW4, SW6, and SW7 are turned off. At this time, a voltage (a first potential) of the first signal line OUTA becomes (+Vs/2), while a voltage (a second potential) of the second signal line OUTB and a voltage of the output line OUTC become a ground level (point in time t1).
Then, by turning on the switch SW6 in the power recovery circuit 21, L-C resonance occurs between the coil L1 and the capacitance of the load 20, and the electric charge recovered in the capacitor C2 is supplied to the load 20 via the switch SW6 and the coil L1 (point in time t2). This current flow causes the voltage of the output line OUTC applied to the common electrode X to increase gradually as shown by a period between points in time t2 and t3. Further, at the point in time t2, the switch SW5 is turned off.
Subsequently, by turning on the switch SW4 in the neighborhood of a peak voltage generated during this resonance (more specifically, just before the voltage reaches the voltage (+Vs/2) after increasing from the ground level), the voltage of the output line OUTC applied to the common electrode X is clamped to (Vs/2) (point in time t3). Further, at the point in time t3, the switch SW6 is turned off.
When the voltage of the output line OUTC applied to the common electrode X is changed from (Vs/2) to the ground level (0 V), first the switch SW7 is turned on, and then the switch SW4 is turned off (point in time t4). As a result, L-C resonance occurs between the coil L2 and the capacitance of the load 20, and part of the electric charge stored in the load 20 is recovered into the capacitor C2 in the power recovery circuit 21. This current flow causes the voltage of the output line OUTC applied to the common electrode X to decrease gradually as shown by a period between points in time t4 and t5.
Then, by turning on the switch SW5 in the neighborhood of a peak voltage (a peak in a minus direction) generated during this resonance, the voltage of the output line OUTC applied to the common electrode X is clamped to the ground level (point in time t5). Also, at the point in time t5, the switch SW7 is turned off.
Next, the switches SW1, SW3, and SW5 are turned off, and the switches SW2 and SW4 are turned on. The switches SW6 and SW7 remain off. Accordingly, the voltages of the first signal line OUTA and the output line OUTC become the ground level, and the voltage of the second signal line OUTB becomes (−Vs/2) (point in time t6).
Then, by turning on the switch SW7 in the power recovery circuit 21, L-C resonance occurs between the coil L2 and the capacitance of the load 20, and the electric charge (minus side) recovered in the capacitor C2 is supplied to the load 20 via the switch SW7 and the coil L2. This current flow causes the voltage of the output line OUTC applied to the common electrode X to decrease gradually as shown by a period between points in time t7 and t8. Moreover, at the point in time t7, the switch SW4 is turned off.
Thereafter, by turning on the switch SW5 in the neighborhood of a peak voltage (a peak in the minus direction) generated during this resonance (more specifically, just before the voltage reaches the voltage (−Vs/2) after decreasing from the ground level), the voltage of the output line OUTC applied to the common electrode X is clamped to (−Vs/2) (point in time t8). Further, at the point in time t8, the switch SW7 is turned off.
When the voltage of the output line OUTC applied to the common electrode X is changed from (−Vs/2) to the ground level (0 V), first, the switch SW6 is turned on, and then the switch SW5 is turned off (point in time t9). As a result, L-C resonance occurs between the coil L1 and the capacitance of the load 20, and part of the electric charge stored in the load 20 is recovered into the capacitor C2 in the power recovery circuit 21. This current flow causes the voltage of the output line OUTC applied to the common electrode X to increase gradually as shown by a period between points in time t9 and t10.
Then, by turning on the switch SW4 in the neighborhood of a peak voltage generated during this resonance, the voltage of the output line OUTC applied to the common electrode X is clamped to the ground level (point in time t10). Also, at the point in time t10, the switch SW6 is turned off.
The driving circuit (TERES circuit) shown in FIG. 18 applies a voltage which changes from (−Vs/2) to (Vs/2) to the common electrode X during the sustain discharge period. Further, it applies voltages (+Vs/2, −Vs/2) each having a polarity opposite to the voltage supplied to the common electrode X are alternately applied to the scan electrode Y on each display line. Thus, the AC-driven PDP device 1 can perform sustain discharge.
Incidentally, during the sustain discharge period, wall charges having opposite polarities needed for sustain discharge are stored in protective film surfaces on the common electrode X and the scan electrode Y. When the discharge is performed between the common electrode X and the scan electrode Y, the wall charges on the common electrode X and the scan electrode Y in the cell respectively become wall charges having polarities opposite to those up to this time to thereby complete the discharge. On this occasion, time for the wall charges to move is needed, and this time is determined by a period of time when the voltage (+Vs/2) or the voltage (−Vs/2) is applied to the common electrode X.